Alioth Code Coverage

Home / Commit 4575b33 / alioth/src/arch/aarch64/reg.rs

reg.rs0.00%

1// Copyright 2024 Google LLC
2//
3// Licensed under the Apache License, Version 2.0 (the "License");
4// you may not use this file except in compliance with the License.
5// You may obtain a copy of the License at
6//
7// https://www.apache.org/licenses/LICENSE-2.0
8//
9// Unless required by applicable law or agreed to in writing, software
10// distributed under the License is distributed on an "AS IS" BASIS,
11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12// See the License for the specific language governing permissions and
13// limitations under the License.
14
15use bitfield::bitfield;
16
17use crate::{bitflags, consts};
18
19#[derive(Debug, Copy, Clone, PartialEq, Eq)]
20pub enum Reg {
21 X0,
22 X1,
23 X2,
24 X3,
25 X4,
26 X5,
27 X6,
28 X7,
29 X8,
30 X9,
31 X10,
32 X11,
33 X12,
34 X13,
35 X14,
36 X15,
37 X16,
38 X17,
39 X18,
40 X19,
41 X20,
42 X21,
43 X22,
44 X23,
45 X24,
46 X25,
47 X26,
48 X27,
49 X28,
50 X29,
51 X30,
52 Sp,
53 Pc,
54 Pstate,
55}
56
57pub const fn encode(op0: u16, op1: u16, crn: u16, crm: u16, op2: u16) -> u16 {
58 (op0 << 14) | (op1 << 11) | (crn << 7) | (crm << 3) | op2
59}
60
61consts! {
62 /// https://developer.arm.com/documentation/ddi0601/2020-12/Index-by-Encoding
63 pub struct SReg(u16) {
64 /// OS Lock Access Register
65 /// https://developer.arm.com/documentation/ddi0601/latest/AArch64-Registers/OSLAR-EL1--OS-Lock-Access-Register
66 OSLAR_EL1 = encode(2, 0, 1, 0, 4);
67 /// OS Double Lock Register
68 /// https://developer.arm.com/documentation/ddi0601/latest/AArch64-Registers/OSDLR-EL1--OS-Double-Lock-Register
69 OSDLR_EL1 = encode(2, 0, 1, 3, 4);
70 /// Multiprocessor Affinity Register
71 MPIDR_EL1 = encode(3, 0, 0, 0, 5);
72 /// System Control Register
73 /// https://developer.arm.com/documentation/ddi0601/latest/AArch64-Registers/SCTLR-EL1--System-Control-Register--EL1-
74 SCTLR_EL1 = encode(3, 0, 1, 0, 0);
75 /// Stack Pointer (EL0)
76 SP_EL0 = encode(3, 0, 4, 1, 0);
77 /// Exception Syndrome Register (EL2)
78 ESR_EL2 = encode(3, 4, 5, 2, 0);
79 }
80}
81
82// https://developer.arm.com/documentation/den0024/a/ARMv8-Registers/Processor-state
83bitflags! {
84 pub struct Pstate(u32) {
85 /// Negative condition flag.
86 N = 1 << 31;
87 /// Zero condition flag.
88 Z = 1 << 30;
89 /// Carry condition flag.
90 C = 1 << 29;
91 /// oVerflow condition flag.
92 V = 1 << 28;
93 /// Debug mask bit.
94 /// Software Step bit.
95 SS = 1 << 21;
96 /// Illegal execution state bit.
97 IL = 1 << 20;
98 D = 1 << 9;
99 /// SError mask bit.
100 A = 1 << 8;
101 /// IRQ mask bit.
102 I = 1 << 7;
103 /// FIQ mask bit.
104 F = 1 << 6;
105 M = 1 << 4;
106
107 EL_BIT3 = 1 << 3;
108 EL_BIT2 = 1 << 2;
109 EL_H = 1 << 0;
110 }
111}
112
113bitfield! {
114 /// Exception Syndrome Register (EL2)
115 ///
116 /// https://developer.arm.com/documentation/ddi0595/2020-12/AArch64-Registers/ESR-EL2--Exception-Syndrome-Register--EL2-
117 #[derive(Copy, Clone, Default, PartialEq, Eq, Hash)]
118 #[repr(transparent)]
119 pub struct EsrEl2(u64);
120 impl Debug;
121 pub iss2, _: 36, 32;
122 pub u8, into EsrEl2Ec, ec, _: 31, 26;
123 pub il, _: 25;
124 pub u32, iss, _: 24, 0;
125}
126
127consts! {
128 pub struct EsrEl2Ec(u8) {
129 HVC_64 = 0x16;
130 SYS_REG_64 = 0x18;
131 INSTR_ABRT_LOWER = 0x20;
132 DATA_ABORT_LOWER = 0x24;
133 }
134}
135
136bitfield! {
137 #[derive(Copy, Clone, Default, PartialEq, Eq, Hash)]
138 pub struct EsrEl2DataAbort(u32);
139 impl Debug;
140 pub isv, _: 24;
141 pub sas, _: 23, 22;
142 pub sse, _: 21;
143 pub srt, _: 20, 16;
144 pub sf, _: 15;
145 pub ar, _: 14;
146 pub vncr, _: 13;
147 pub set, _: 12, 11;
148 pub fnv, _: 10;
149 pub ea, _: 9;
150 pub cm, _: 8;
151 pub s1ptw, _: 7;
152 pub wnr, _: 6;
153 pub dfsc, _: 5, 0;
154}
155
156bitfield! {
157 #[derive(Copy, Clone, Default, PartialEq, Eq, Hash)]
158 pub struct EsrEl2SysReg(u32);
159 impl Debug;
160 pub is_read, _: 0;
161 pub u16, crm, _: 4, 1;
162 pub rt, _: 9, 5;
163 pub u16, crn, _: 13, 10;
164 pub u16, op1, _: 16, 14;
165 pub u16, op2, _: 19, 17;
166 pub u16, op0, _: 21, 20;
167}
168
169bitfield! {
170 #[derive(Copy, Clone, Default, PartialEq, Eq, Hash)]
171 pub struct MpidrEl1(u64);
172 impl Debug;
173 pub u8, aff3, set_aff3: 39, 32;
174 pub u, set_u: 30;
175 pub mt, set_mt: 24;
176 pub u8, aff2, set_aff2: 23, 16;
177 pub u8, aff1, set_aff1: 15, 8;
178 pub u8, aff0, set_aff0: 7, 0;
179}
180