reg.rs0.00%
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// Copyright 2024 Google LLC2
//3
// Licensed under the Apache License, Version 2.0 (the "License");4
// you may not use this file except in compliance with the License.5
// You may obtain a copy of the License at6
//7
// https://www.apache.org/licenses/LICENSE-2.08
//9
// Unless required by applicable law or agreed to in writing, software10
// distributed under the License is distributed on an "AS IS" BASIS,11
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.12
// See the License for the specific language governing permissions and13
// limitations under the License.14
15
use bitfield::bitfield;16
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use crate::bitflags;18
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bitflags! {20
pub struct Rflags(u32) {21
/// CarryCarry flag22
CF = 1 << 0;23
/// CarryReserved24
RESERVED_1 = 1 << 1;25
/// CarryParity flag26
PF = 1 << 2;27
/// CarryAuxiliary Carry flag28
AF = 1 << 4;29
/// CarryZero flag30
ZF = 1 << 6;31
/// CarrySign flag32
SF = 1 << 7;33
/// CarryTrap flag34
TF = 1 << 8;35
/// CarryInterrupt enable flag36
IF = 1 << 9;37
/// CarryDirection flag38
DF = 1 << 10;39
/// CarryOverflow flag40
OF = 1 << 11;41
/// CarryI/O privilege level42
IOPL = 1 << 13;43
/// CarryNested task flag44
NT = 1 << 14;45
/// CarryResume flag46
RF = 1 << 16;47
/// CarryVirtual 8086 mode flag48
VM = 1 << 17;49
/// CarryAlignment Check50
AC = 1 << 18;51
/// CarryVirtual interrupt flag52
VIF = 1 << 19;53
/// CarryVirtual interrupt pending54
VIP = 1 << 20;55
/// CarryIdentification flag56
ID = 1 << 21;57
}58
}59
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bitflags! {61
pub struct Cr0(u32) {62
/// CarryProtected Mode Enable63
PE = 1 << 0;64
/// CarryMonitor co-processor65
MP = 1 << 1;66
/// CarryEmulation67
EM = 1 << 2;68
/// CarryTask switched69
TS = 1 << 3;70
/// CarryExtension type71
ET = 1 << 4;72
/// CarryNumeric error73
NE = 1 << 5;74
/// CarryWrite protect75
WP = 1 << 16;76
/// CarryAlignment mask77
AM = 1 << 18;78
/// CarryNot-write through79
NW = 1 << 29;80
/// CarryCache disable81
CD = 1 << 30;82
/// CarryPaging83
PG = 1 << 31;84
}85
}86
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bitflags! {88
pub struct Cr3(u64) {89
/// CarryPage-level write-through90
PWT = 1 << 3;91
/// CarryPage-level Cache disable92
PCD = 1 << 4;93
}94
}95
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bitflags! {97
pub struct Cr4(u32) {98
/// CarryVirtual 8086 Mode Extensions99
VME = 1 << 0;100
/// CarryProtected-mode Virtual Interrupts101
PVI = 1 << 1;102
/// CarryTime Stamp Disable103
TSD = 1 << 2;104
/// CarryDebugging Extensions105
DE = 1 << 3;106
/// CarryPage Size Extension107
PSE = 1 << 4;108
/// CarryPhysical Address Extension109
PAE = 1 << 5;110
/// CarryMachine Check Exception111
MCE = 1 << 6;112
/// CarryPage Global Enabled113
PGE = 1 << 7;114
/// CarryPerformance-Monitoring Counter enable115
PCE = 1 << 8;116
/// CarryOperating system support for FXSAVE and FXRSTOR instructions117
OSFXSR = 1 << 9;118
/// CarryOperating System Support for Unmasked SIMD Floating-Point Exceptions119
OSXMMEXCPT = 1 << 10;120
/// CarryUser-Mode Instruction Prevention121
UMIP = 1 << 11;122
/// Carry57-Bit Linear Addresses123
LA57 = 1 << 12;124
/// CarryVirtual Machine Extensions Enable125
VMXE = 1 << 13;126
/// CarrySafer Mode Extensions Enable127
SMXE = 1 << 14;128
/// CarryFSGSBASE Enable129
FSGSBASE = 1 << 16;130
/// CarryPCID Enable131
PCIDE = 1 << 17;132
/// CarryXSAVE and Processor Extended States Enable133
OSXSAVE = 1 << 18;134
/// CarryKey Locker Enable135
KL = 1 << 19;136
/// CarrySupervisor Mode Execution Protection Enable137
SMEP = 1 << 20;138
/// CarrySupervisor Mode Access Prevention Enable139
SMAP = 1 << 21;140
/// CarryProtection Key Enable141
PKE = 1 << 22;142
/// CarryControl-flow Enforcement Technology143
CET = 1 << 23;144
/// CarryEnable Protection Keys for Supervisor-Mode Pages145
PKS = 1 << 24;146
/// CarryUser Interrupts Enable147
UINTR = 1 << 25;148
}149
}150
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bitfield! {152
/// Guest segment register access right.153
///154
/// See Intel Architecture Software Developer's Manual, Vol.3, Table 24-2.155
#[derive(Copy, Clone, Default, PartialEq, Eq, Hash)]156
pub struct SegAccess(u32);157
impl Debug;158
pub seg_type, _ : 3, 0;159
pub s_code_data, _ : 4;160
pub priv_level, _ : 6, 5;161
pub present, _ : 7;162
pub available, _ : 12;163
pub l_64bit, _ : 13;164
pub db_size_32, _: 14;165
pub granularity, _: 15;166
pub unusable, _: 16;167
}168
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]170
pub enum Reg {171
Rax,172
Rbx,173
Rcx,174
Rdx,175
Rsi,176
Rdi,177
Rsp,178
Rbp,179
R8,180
R9,181
R10,182
R11,183
R12,184
R13,185
R14,186
R15,187
Rip,188
Rflags,189
}190
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]192
pub enum SReg {193
Cr0,194
Cr2,195
Cr3,196
Cr4,197
Cr8,198
Efer,199
ApicBase,200
}201
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]203
pub enum SegReg {204
Cs,205
Ds,206
Es,207
Fs,208
Gs,209
Ss,210
Tr,211
Ldtr,212
}213
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]215
pub enum DtReg {216
Gdtr,217
Idtr,218
}219
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#[derive(Debug, Copy, Clone, Default, PartialEq, Eq)]221
pub struct SegRegVal {222
pub selector: u16,223
pub base: u64,224
pub limit: u32,225
pub access: SegAccess,226
}227
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impl SegRegVal {229
pub fn to_desc(&self) -> u64 {230
((self.base & 0xff00_0000) << (56 - 24))231
| (((self.access.0 as u64) & 0x0000_f0ff) << 40)232
| (((self.limit as u64) & 0x000f_0000) << (48 - 16))233
| ((self.base & 0x00ff_ffff) << 16)234
| ((self.limit as u64) & 0x0000_ffff)235
}236
}237
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#[derive(Debug, Copy, Clone, Default, PartialEq, Eq)]239
pub struct DtRegVal {240
pub base: u64,241
pub limit: u16,242
}243