Alioth Code Coverage

reg.rs0.00%

1// Copyright 2024 Google LLC
2//
3// Licensed under the Apache License, Version 2.0 (the "License");
4// you may not use this file except in compliance with the License.
5// You may obtain a copy of the License at
6//
7// https://www.apache.org/licenses/LICENSE-2.0
8//
9// Unless required by applicable law or agreed to in writing, software
10// distributed under the License is distributed on an "AS IS" BASIS,
11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12// See the License for the specific language governing permissions and
13// limitations under the License.
14
15use bitfield::bitfield;
16
17use crate::bitflags;
18
19bitflags! {
20 pub struct Rflags(u32) {
21 /// CarryCarry flag
22 CF = 1 << 0;
23 /// CarryReserved
24 RESERVED_1 = 1 << 1;
25 /// CarryParity flag
26 PF = 1 << 2;
27 /// CarryAuxiliary Carry flag
28 AF = 1 << 4;
29 /// CarryZero flag
30 ZF = 1 << 6;
31 /// CarrySign flag
32 SF = 1 << 7;
33 /// CarryTrap flag
34 TF = 1 << 8;
35 /// CarryInterrupt enable flag
36 IF = 1 << 9;
37 /// CarryDirection flag
38 DF = 1 << 10;
39 /// CarryOverflow flag
40 OF = 1 << 11;
41 /// CarryI/O privilege level
42 IOPL = 1 << 13;
43 /// CarryNested task flag
44 NT = 1 << 14;
45 /// CarryResume flag
46 RF = 1 << 16;
47 /// CarryVirtual 8086 mode flag
48 VM = 1 << 17;
49 /// CarryAlignment Check
50 AC = 1 << 18;
51 /// CarryVirtual interrupt flag
52 VIF = 1 << 19;
53 /// CarryVirtual interrupt pending
54 VIP = 1 << 20;
55 /// CarryIdentification flag
56 ID = 1 << 21;
57 }
58}
59
60bitflags! {
61 pub struct Cr0(u32) {
62 /// CarryProtected Mode Enable
63 PE = 1 << 0;
64 /// CarryMonitor co-processor
65 MP = 1 << 1;
66 /// CarryEmulation
67 EM = 1 << 2;
68 /// CarryTask switched
69 TS = 1 << 3;
70 /// CarryExtension type
71 ET = 1 << 4;
72 /// CarryNumeric error
73 NE = 1 << 5;
74 /// CarryWrite protect
75 WP = 1 << 16;
76 /// CarryAlignment mask
77 AM = 1 << 18;
78 /// CarryNot-write through
79 NW = 1 << 29;
80 /// CarryCache disable
81 CD = 1 << 30;
82 /// CarryPaging
83 PG = 1 << 31;
84 }
85}
86
87bitflags! {
88 pub struct Cr3(u64) {
89 /// CarryPage-level write-through
90 PWT = 1 << 3;
91 /// CarryPage-level Cache disable
92 PCD = 1 << 4;
93 }
94}
95
96bitflags! {
97 pub struct Cr4(u32) {
98 /// CarryVirtual 8086 Mode Extensions
99 VME = 1 << 0;
100 /// CarryProtected-mode Virtual Interrupts
101 PVI = 1 << 1;
102 /// CarryTime Stamp Disable
103 TSD = 1 << 2;
104 /// CarryDebugging Extensions
105 DE = 1 << 3;
106 /// CarryPage Size Extension
107 PSE = 1 << 4;
108 /// CarryPhysical Address Extension
109 PAE = 1 << 5;
110 /// CarryMachine Check Exception
111 MCE = 1 << 6;
112 /// CarryPage Global Enabled
113 PGE = 1 << 7;
114 /// CarryPerformance-Monitoring Counter enable
115 PCE = 1 << 8;
116 /// CarryOperating system support for FXSAVE and FXRSTOR instructions
117 OSFXSR = 1 << 9;
118 /// CarryOperating System Support for Unmasked SIMD Floating-Point Exceptions
119 OSXMMEXCPT = 1 << 10;
120 /// CarryUser-Mode Instruction Prevention
121 UMIP = 1 << 11;
122 /// Carry57-Bit Linear Addresses
123 LA57 = 1 << 12;
124 /// CarryVirtual Machine Extensions Enable
125 VMXE = 1 << 13;
126 /// CarrySafer Mode Extensions Enable
127 SMXE = 1 << 14;
128 /// CarryFSGSBASE Enable
129 FSGSBASE = 1 << 16;
130 /// CarryPCID Enable
131 PCIDE = 1 << 17;
132 /// CarryXSAVE and Processor Extended States Enable
133 OSXSAVE = 1 << 18;
134 /// CarryKey Locker Enable
135 KL = 1 << 19;
136 /// CarrySupervisor Mode Execution Protection Enable
137 SMEP = 1 << 20;
138 /// CarrySupervisor Mode Access Prevention Enable
139 SMAP = 1 << 21;
140 /// CarryProtection Key Enable
141 PKE = 1 << 22;
142 /// CarryControl-flow Enforcement Technology
143 CET = 1 << 23;
144 /// CarryEnable Protection Keys for Supervisor-Mode Pages
145 PKS = 1 << 24;
146 /// CarryUser Interrupts Enable
147 UINTR = 1 << 25;
148 }
149}
150
151bitfield! {
152 /// Guest segment register access right.
153 ///
154 /// See Intel Architecture Software Developer's Manual, Vol.3, Table 24-2.
155 #[derive(Copy, Clone, Default, PartialEq, Eq, Hash)]
156 pub struct SegAccess(u32);
157 impl Debug;
158 pub seg_type, _ : 3, 0;
159 pub s_code_data, _ : 4;
160 pub priv_level, _ : 6, 5;
161 pub present, _ : 7;
162 pub available, _ : 12;
163 pub l_64bit, _ : 13;
164 pub db_size_32, _: 14;
165 pub granularity, _: 15;
166 pub unusable, _: 16;
167}
168
169#[derive(Debug, Copy, Clone, PartialEq, Eq)]
170pub enum Reg {
171 Rax,
172 Rbx,
173 Rcx,
174 Rdx,
175 Rsi,
176 Rdi,
177 Rsp,
178 Rbp,
179 R8,
180 R9,
181 R10,
182 R11,
183 R12,
184 R13,
185 R14,
186 R15,
187 Rip,
188 Rflags,
189}
190
191#[derive(Debug, Copy, Clone, PartialEq, Eq)]
192pub enum SReg {
193 Cr0,
194 Cr2,
195 Cr3,
196 Cr4,
197 Cr8,
198 Efer,
199 ApicBase,
200}
201
202#[derive(Debug, Copy, Clone, PartialEq, Eq)]
203pub enum SegReg {
204 Cs,
205 Ds,
206 Es,
207 Fs,
208 Gs,
209 Ss,
210 Tr,
211 Ldtr,
212}
213
214#[derive(Debug, Copy, Clone, PartialEq, Eq)]
215pub enum DtReg {
216 Gdtr,
217 Idtr,
218}
219
220#[derive(Debug, Copy, Clone, Default, PartialEq, Eq)]
221pub struct SegRegVal {
222 pub selector: u16,
223 pub base: u64,
224 pub limit: u32,
225 pub access: SegAccess,
226}
227
228impl SegRegVal {
229 pub fn to_desc(&self) -> u64 {
230 ((self.base & 0xff00_0000) << (56 - 24))
231 | (((self.access.0 as u64) & 0x0000_f0ff) << 40)
232 | (((self.limit as u64) & 0x000f_0000) << (48 - 16))
233 | ((self.base & 0x00ff_ffff) << 16)
234 | ((self.limit as u64) & 0x0000_ffff)
235 }
236}
237
238#[derive(Debug, Copy, Clone, Default, PartialEq, Eq)]
239pub struct DtRegVal {
240 pub base: u64,
241 pub limit: u16,
242}
243